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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT563 Octal D-type transparent latch; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting FEATURES * 3-state inverting outputs for bus oriented applications * Inputs and outputs on opposite sides of package allowing easy interface with microprocessor * Common 3-state output enable input * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch and inverting 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The "563" is functionally identical to the "573", but has inverted outputs. The "563" consists of eight D-type transparent latches with 3-state inverting outputs. The LE and OE are 74HC/HCT563 common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC for HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay Dn, LE to Qn input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 3.5 19 HCT 16 3.5 19 ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting PIN DESCRIPTION PIN NO. 2, 3, 4, 5, 6, 7, 8, 9 11 1 10 19, 18, 17, 16, 15, 14, 13, 12 20 SYMBOL D0 to D7 LE OE GND Q0 to Q7 VCC NAME AND FUNCTION data inputs 74HC/HCT563 latch enable input (active HIGH) 3-state output enable input (active LOW) ground (0 V) 3-state latch outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting FUNCTION TABLE INPUTS OPERATING MODES OE LE enable and read register latch and read register latch register and disable outputs Notes L L L L H H H H L L L L Dn L H l h l h 74HC/HCT563 INTERNAL LATCHES L H L H L H OUTPUTS Q0 to Q7 H L H L Z Z Fig.4 Functional diagram. 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT563 TEST CONDITIONS UNIT V CC WAVEFORMS (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 +25 min. typ. 47 17 14 47 17 14 47 17 14 50 18 14 14 5 4 80 16 14 50 10 9 4 4 4 14 5 4 11 4 3 -6 -2 -2 max. 145 29 25 145 29 25 150 30 26 150 30 26 60 12 10 -40 to +85 min. max. 180 36 31 180 36 31 190 38 33 190 38 33 75 15 13 100 20 17 65 13 11 4 4 4 -40 to +125 min. max. 220 44 38 220 44 38 225 45 38 225 45 38 90 18 15 120 24 20 75 15 13 4 4 4 tPHL/ tPLH propagation delay Dn to Qn tPHL/ tPLH propagation delay LE to Qn tPZH/ tPZL 3-state output enable time OE to Qn tPHZ/ tPLZ 3-state output disable time OE to Qn tTHL/ tTLH output transition time ns Fig.7 ns Fig.8 ns Fig.8 ns Fig.6 tW enable pulse width HIGH set-up time Dn to LE hold time Dn to LE ns Fig.7 tsu ns Fig.9 th ns Fig.9 December 1990 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT563 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn LE OE UNIT LOAD COEFFICIENT 0.35 0.65 1.25 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time enable pulse width HIGH set-up time Dn to LE hold time Dn to LE 16 10 5 +25 typ. 18 19 20 22 5 5 3 -1 max. 30 35 35 35 12 20 13 5 -40 to +85 min. max. 38 44 44 44 15 24 15 5 -40 to +125 min. max. 45 53 53 53 18 ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.8 Fig.8 Fig.6 Fig.7 Fig.9 Fig.9 UNIT V CC WAVEFORMS (V) TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting AC WAVEFORMS 74HC/HCT563 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data input (Dn) to output (Qn) propagation delays and the output transition times. Fig.7 Waveforms showing the latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the data set-up and hold times for Dn input to LE input PACKAGE OUTLINES (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. See "74HC/HCT/HCU/HCMOS Logic Package Outlines". Fig.8 Waveforms showing the 3-state enable and disable times. December 1990 7 This datasheet has been download from: www..com Datasheets for electronics components. |
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